Figure 4.12: Multislot power versus time mask for the NB and for the AB— (a) power level is higher on first time slot; and (b) power level is higher on second time slot.
Figure 4.13: Circuit for a convolutional code.
Figure 4.14: Circuit for the rate 1/2 code defined by G0 and G1.
Figure 4.15: Example with the input bit sequence 1 0 0 1.
Figure 4.16: Discrete memoryless channel.
Figure 4.17: Example of 1/2 convolutional code.
Figure 4.18: Associated trellis diagram for the example code.
Figure 4.19: Representation of the survivors at step 5.
Figure 4.20: BER estimation for the RXQUAL measurement— operations in the (a) transmitter and (b) receiver.
Figure 4.21: IF receiver architecture.
Figure 4.22: Problem of image frequency in IF architecture.
Figure 4.23: Zero-IF receiver architecture.
Figure 4.24: The dc offset sources in the ZIF receiver—